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august 2006 rev 1 1/53 1 M65KA128AE 128mbit (4 banks x 2m x 16) 1.8 v supply, low power sdram features summary 128mbit synchronous dynamic ram ? organized as 4 banks of 2mwords, each 16 bits wide synchronous burst read and write ? fixed burst lengths: 1, 2, 4, 8 words or full page ? burst types: sequential and interleaved. ? maximum clock frequency: 133mhz ? clock valid to output delay (cas latency): 3 at maximum clock frequency ? burst control by burst stop and precharge command supply voltage ?v dd = v ddq = 1.7 to 1.95v automatic and controlled precharge byte control by ldqm and udqm low-power features: ? partial array self refresh (pasr), ? automatic temperature compensated self refresh (tcsr) ? driver strength (ds) ? deep power-down mode auto refresh and self refresh lvcmos interface compatible with multiplexed addressing operating temperature range ? ? 25 to 90c M65KA128AE is only available as part of a multiple memory product wafer www.st.com
contents M65KA128AE 2/53 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 address inputs (a0-a11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 bank select address inputs (ba0-ba1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 data inputs/outputs (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 chip select (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 column address strobe (cas) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 row address strobe (ras) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 write enable (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 clock input (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 clock enable (ke) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 lower/upper data input/output mask (ldqm, udqm) . . . . . . . . . . . . . . 10 2.11 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.12 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.13 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.14 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 deep power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 mode register set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 extended mode register set command . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 bank (row) activate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
M65KA128AE contents 3/53 4.5 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 auto precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 burst stop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9 data mask command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.10 clock suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.11 auto refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.12 self refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.13 power-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.14 deep power-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 burst length bits (mr0 to mr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 burst type bit (mr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 cas latency bits (mr4 to mr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 extended mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5.1 partial array self refresh bits (emr0-emr2) . . . . . . . . . . . . . . . . . . . . 20 5.5.2 driver strength bit (emr5-emr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5.3 automatic temperature compensated self refresh bits(emr3-emr4) 21 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
list of figures M65KA128AE 4/53 list of figures figure 1. logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. ac measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 figure 4. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. chip enable signal during read, write and precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 6. read with precharge ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7. read with auto precharge ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 8. clock suspend during burst read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 9. random column read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 10. random row read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 11. column interleaved read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 12. burst column read followed by auto precharge ac waveforms . . . . . . . . . . . . . . . . . . . 35 figure 13. write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 14. byte write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 15. mode register set ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 figure 16. clock suspend during burst write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 17. random column write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 18. random row write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 19. column interleaved write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 20. burst column write followed by auto precharge ac waveforms . . . . . . . . . . . . . . . . . . . 43 figure 21. precharge termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 22. power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 23. power-down mode and clock masking ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 24. auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 25. self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 26. deep power-down entry ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 27. deep power-down exit ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
M65KA128AE list of tables 5/53 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. extended mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. dc characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. dc characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. self-refresh current (i dd6 ) values in normal operating mode . . . . . . . . . . . . . . . . . . . . . 26 table 12. ac characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. ac characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 14. ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 15. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
summary description M65KA128AE 6/53 1 summary description the M65KA128AE is a 128mbit low power synchronous dram (sdram). the memory array is organized as 4 banks of 2,097,152 words of 16 bits each. the lpsdram achieves low power consumption and high-speed data transfer using the pipeline architecture. it is well suited for handheld battery powered applications like pdas, 2.5 and 3g mobile phones and handheld computers. the device architecture is illustrated in figure 2: functional block diagram . it uses burst mode to read and write data. it is capable of one, two, four, eight-word and full-page, sequential and interleaved burst. to minimize current consumption during self-r efresh operations, the M65KA128AE includes three mechanisms configured via the extended mode register: automatic temperature compensated self refresh (atcsr) used to adapt the refresh time according to the operating temperature (see table 5: extended mode register definition ) partial array self refresh (pasr) performs a limited refresh of part of the psram memory array. this area can be configured to half bank, a quarter of bank, one bank, two banks or all banks. this mechanism allows to reduce the device standby current by refreshing only the part of the memory array that contains essential data. the deep power-down (dpd) mode completely halts the refresh operation and achieves minimum current consumption by cutting off the supply voltage from the whole memory array. the device is programmable through two registers, the mode register and the extended mode register: the mode register is used to select the cas latency, the burst type (sequential, interleaved) and the burst length (1-, 2-, 4-, 8-word width or full page) through programming the a6 to a4 bits, the a3 bit and the a2 to a0 bits, respectively (see ta bl e 4 ). the extended mode register is used to program the low-power features (pasr, atcsr) and driver strength) to reduce the current consumption during the self refresh operations. for more details, refer to table 5: extended mode register definition , and to section 4.2: extended mode register set command .
M65KA128AE summary description 7/53 figure 1. logic diagram table 1. signal names a0-a11 address inputs ba0-ba1 bank select inputs dq0-dq15 data inputs/outputs k clock input ke clock enable input e chip select input w write enable input ras row address strobe input cas column address strobe input udqm upper data input/output mask ldqm lower data input/output mask v dd supply voltage v ddq input/output s upply voltage v ss ground v ssq input/output ground ai12170 12 a0-a11 dq0-dq15 v dd M65KA128AE e cas v ss 16 ras v ddq ba0-ba1 2 k ke w v ssq udqm ldqm
summary description M65KA128AE 8/53 figure 2. functional block diagram extended mode register tcsr, pasr self refresh logic & timer internal row counter row pre- decoders k ke e ras cas w u/ldqm state machine refresh column active bank select address registers address buffers 2 mb x 16 bank 2 mb x 16 bank 2 2 mb x 16 bank 1 2 mb x 16 bank 0 row decoders row decoders row decoders row decoders memory cell array column decoders sense amp & i/o gate i/o buffer & logic dq0 dq15 ... ... ... column pre- decoders ... a0 a1 a11 ba1 ba0 ... column add counter mode register cas latency data out control burst counter burst length ai12171 row active
M65KA128AE signal descriptions 9/53 2 signal descriptions see figure 1: logic diagram , and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a11) the a0-a11 address inputs are used to select the row or column to be made active. if a row is selected, all thirteen, a0-a11 address inputs are used. if a column is selected, only the nine least significant address inputs, a0-a8, are used. in this latter case, a10 determines whether auto precharge is used. if a10 is high (set to ?1?) during read or write, the read or write operation includes an auto precharge cycle. if a10 is low (set to ?0?) during read or write, the read or write cycle does not include an auto precharge cycle. 2.2 bank select address inputs (ba0-ba1) the ba0 and ba1 banks select address inputs select the bank to be made active. the device must be enabled, the row address strobe, ras , must be low, v il , the column address strobe, cas , and w must be high, v ih , when selecting the addresses. the address inputs are latched on the rising edge of the clock signal, k. 2.3 data inputs/outputs (dq0-dq15) the data inputs/outputs output the data stored at the selected address during a read operation, or are used to input the data during a write operation. 2.4 chip select (e ) the chip select input e activates the memory state machine, address buffers and decoders when driven low, v il . when high, v ih , the device is not selected. 2.5 column address strobe (cas ) the column address strobe, cas , is used in conjunction with address inputs a8-a0 and ba1-ba0, to select the starting column location prior to a read or write. 2.6 row address strobe (ras ) the row address strobe, ras , is used in conjunction with address inputs a11-a0 and ba1-ba0, to select the starting address location prior to a read or write. 2.7 write enable (w ) the write enable input, w , controls writing.
signal descriptions M65KA128AE 10/53 2.8 clock input (k) the clock signal, k, is used to clock the read and write cycles. during normal operation, the clock enable pin, ke, is high, v ih . the clock signal k can be suspended to switch the device to the self-refresh, power-down or deep power-down mode by driving ke low, v il . 2.9 clock enable (ke) the clock enable, ke, pin is used to control the synchronizing of the signals with clock signal k. if ke is high, v ih , the next clock rising edge is valid. when ke is low, v il , the signals are no longer clocked and data read and write cycles are extended. ke is also involved in switching the device to the se lf-refresh, power-down and deep power-down modes. 2.10 lower/upper data input/ output mask (ldqm, udqm) lower data input/output mask and upper data input/output mask pins are input signals used to mask the read or write data. the dqm latency is two clock cycles for read operations and there is no latency for write operations. 2.11 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read and write). 2.12 v ddq supply voltage v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently of v dd . v ddq can be tied to v dd or can use a separate supply. it is recommended to power-up and power-down v dd and v ddq together to avoid certain conditions that would result in data corruption. 2.13 v ss ground ground, v ss, is the reference for the core power supply. it must be connected to the system ground. 2.14 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss . note: each device in a system should have v dd and v ddq decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, inhere ntly low inductance capacitors should be as close as possible to the package).
M65KA128AE operations 11/53 3 operations there are 7 operating modes that control the memory. each of these is described in this section, see table 2: operating modes , for a summary. 3.1 power-up the low-power sdram has to be powered up and initialized in a well determined manner. power must be applied to v dd and v ddq simultaneously and, at the same time, the clock signal must be started. after power-up, a minimum initial pause of 200s is required. from power-up until the precharge command is issued, the ke and dqm signals must be held high. the precharge command must then be issued to all banks, and 2 or more auto refresh cycles must be executed after the precharge is completed and the minimum t rp is satisfied. once these cycles are completed, a mode register set command must be issued to program the specific operation mode (cas latency, burst length, etc.). after issuing the mode register set command, the device will not accept any other command for t rsc . an extended mode register set command must also be issued to program the self refresh operation mode (pasr and ds). after issuing the extended mode register set command the device will not accept any other command for t rsc . the auto refresh, mode register programming and extended mode register programming can be performed in a random sequence. cke and dqm must be held high until the precharge command is issued to ensure the data bus high-z level. the device is now ready for normal operation. refer to figure 22 for a detailed description of the power-up ac waveforms. 3.2 burst read the read command is used to switch the device to burst read mode (see section 4.5: read command for details). in burst read mode the data is output in bursts synchronized with the clock. a valid burst read operation is initiated by driving e and cas low, v il , and w and ras high, v ih , at the positive edge of the clock signal, k. burst read can be accompanied by an auto precharge cycle depending on the state of the a10 address input. if a10 is high (set to ?1?) when the burst read command is issued, the burst read operation will be followed by an auto precharge cycle. if a10 is low (set to ?0?), the row will remain active for subsequent accesses. ba1 and ba0 are used to select the bank, and the a8-a0 address inputs are used to select the starting column location. during a burst read operation, the memory reads data from the activated bank. the burst length (1, 2, 4, 8 words or full page), burst type (sequential or interleaved), and cas latency depend on the values programmed by issuing a mode register set command (see section 5.1: mode register description ). after a burst read operation is completed, data outputs become high-z. refer to figure 6 , figure 7 , figure 8 , figure 9 , figure 10 , figure 11 and figure 12 for a detailed description of burst read ac waveforms.
operations M65KA128AE 12/53 3.3 burst write the write command is used to switch the device to burst write mode (see section 4.4: write command for details). in burst write mode the data is input in bursts synchronized with the clock. a valid burst write initiated by driving e , cas and w low, v il , and ras high, v ih , at the positive edge of the clock signal, k. burst write can be accompanied by an auto precharge cycle depending on the state of the a10 address input. if a10 is high (set to ?1?) when the write command is issued, the write operation will be followed by an au to precharge cycle. if a10 is low (set to ?0?), auto precharge is not selected and the row will remain active for subsequent accesses. ba1 and ba0 are used to select the bank, and the a8-a0 address inputs are used to select the starting column location. during burst write operation, the memory writes data to the activated bank. as for burst read, differen t burst types and leng ths can be utilized, programmed in the same fashion. refer to figure 13 , figure 14 , figure 16 , figure 17 , figure 18 , figure 19 and figure 20 for a detailed description of burst write ac waveforms. 3.4 self refresh in self refresh mode, the data contained in the low-power sdram memory array is retained and refreshed. the low-power sdram refresh cycles are asynchronous. all banks must be precharged prior to executing a self-refresh operation. the self-refresh mode is entered by driving ke low (set to ?0?), with e , ras , and cas low, and w high (set to ?1?). when in this mode, the device is not clocked any more. the self refresh mode is exited by driving ke from low to high, with e high, ras , cas and w don?t care, or with e low and r as , cas and w high. the self refresh operation is performed according to the settings of extended mode register bits emr0 to emr2. they configure the amount of the memory to be refreshed (partial array self refresh). 3.5 auto refresh the auto refresh mode is used to refresh the low-power sdram in normal operation mode whenever needed. all banks must be precharged prior to executing an auto refresh operation. during the auto refresh, ke must be kept high, v ih and the address bits are ?don?t care?, because the specific address bits are generated by the internal refresh address counter.
M65KA128AE operations 13/53 3.6 power-down in power-down mode, the current is reduced to the standby current (i dd3p ). all banks must be precharged before entering power-down mode. for the memory to enter the power-down mode, ke must be held low (set to ?0?), after the precharge time t rp , with e high (set to ?1?), ras , cas and w don?t care, or with e low, ras , cas and w high. the power-down mode is exit ed by driving ke high, with e high, ras , cas and w don?t care, or with e low and ras , cas and w high. 3.7 deep power-down the purpose of this mode is to achieve maximum power reduction by cutting the power supply to the whole memory array. data is no longer retained when the device enters deep power-down mode. all banks must be precharged before entering deep power-down mode. the M65KA128AE enters deep power down mode by holding e and w low with ras and cas high at the rising edge of the clock, k, while driving ke low (see figure 26: deep power-down entry ac waveforms ). the M65KA128AE exits deep power-down mode by asserting ke high. a special sequence is then required before the device can take any new command into account: 1. maintain no operation status conditions for a minimum of 200s, 2. issue a precharge command to all banks of the device (see section 4.6: precharge command for details), 3. issue a mode register set command to initialize the mode register bits, 4. issue an extended mode register set command to initialize the extended mode register bits, 5. issue 2 or more auto refresh commands. the deep power-down mode exit sequence is illustrated in figure 27: deep power-down exit ac waveforms . note: the 2 auto refresh commands can be issued either after or before the configuration of the mode and extended mode registers.
operations M65KA128AE 14/53 table 2. operating modes operating mode e ras (1) cas (1) w (1) ken-1 ken (1) a10 (1) a9, a11 (1) a0-a8 (1) ba0- ba1 (1) udqm/ ldqm (1) burst read v il v ih v il v ih v ih xv il valid start column address bank select valid burst write v il v ih v il v il v ih xv il valid start column address bank select valid self refresh v il v il v il v ih v ih v il xxx auto refresh v il v il v il v ih v ih v ih xxx power-down with precharge v il v ih v ih v ih v ih v il xxx v ih xxx deep power- down v il v ih v ih v il v ih v il xxx device deselect v ih xxxv ih xxx x x x no operation v il v ih v ih v ih v ih xx x 1. x = don?t care v il or v ih .
M65KA128AE commands 15/53 4 commands there are 14 basic commands that control the memory. they can be combined to obtain 21 higher level commands shown in table 3: commands . 4.1 mode register set command the mode register set command is issued by applying v il to e , ras , cas and w and by setting ba1 to ?0?, and ba0 to ?0?. the mode register set command is used to configure the specific mode of operation of the device by programming the mode register: burst length (1, 2, 4, 8, full page) cas latency (2, or 3) burst type (sequential or interleaved). the mode register set command must be executed after the power-up sequence prior to issuing a bank (row) activate command (see figure 15: mode register set ac waveforms ). the execution of a mode register set command will re-program the mode register, modifying its contents. 4.2 extended mode register set command the extended mode register set command is issued by applying v il to e , ras , cas and w , and then by setting ba1 to ?1?, and ba0 to ?0?. the extended mode register set command is used to configure the self refresh operation of the device and the driver strength by programming the extended mode register bits: partial arrays to be refreshed (all banks, two banks, one bank), driver strength (full, 1/2 strength, 1/4 strength, 1/8 strength). the extended mode regi ster bit controlling the automati c tscr (a9) should always be cleared to ?0? (a9 = ?1? is reserved). the extended mode register set command must be executed after the power-up sequence prior to issuing a bank (row) activate command. the execution of an extende d mode register set command will re-program the extended mode register, modifying its contents. 4.3 bank (row) activate command the bank (row) activate command is used to activate a row in a specific bank of the device. this command is initiated by driving e and ras low, v il, and cas and w high, v ih , at the positive edge of the clock signal, k. the value on ba1 and ba0 selects the bank, and the value on a0-a11 selects the row. the selected row remains active for column access until a precharge command is issued to that bank. a minimum time of t rcd is required after issuing the bank (row) active command prior to initiating read and write operations from and to the activated bank.
commands M65KA128AE 16/53 4.4 write command the write command is used to switch the low-power sdram to burst write mode (see section 3.3: burst write mode). 4.5 read command the read command is used to switch the low-power sdram to burst read mode (see section 3.2: burst read ). 4.6 precharge command the precharge command is used to close the open row in a particular bank or the open row in all banks. when the precharge command is issued with address a10 driven high, all banks will be precharged. if a10 is driven lo w, the open row in a particular bank will be precharged. the bank(s) will be available when the minimum t rp time has elapsed after the precharge command has been issued. 4.7 auto precharge command the auto precharge command is used to close the open row in a specific bank after a read or write operation. read or write with auto precharge is initiated if a10 is high, v ih , when a read (or write) command is issued. the t ras must be satisfied with a read with auto precharge or a write with auto precharge operation. in addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. 4.8 burst stop command the burst stop command is used to stop a burst operation. a burst operation can be interrupted by using the precharge command (see section 4.6: precharge command for details), or by issuing the burst stop command. issuing the burst stop command during a burst read or write cycle will stop th e burst while leaving the bank open. 4.9 data mask command the data mask command is used to mask read or write data. a data mask command issued during a read operation will disable t he data outputs, switching them to the high impedance state after a delay of two clock cycles. a data mask command issued during a write operation will disable th e data inputs with no delay.
M65KA128AE commands 17/53 4.10 clock suspend command the clock suspend command is used to interrupt the internal clock of the lpsdram. the command is controlled by the clock enab le input, ke, which is kept high, v ih , in normal access mode. the clock suspend command is issued by driving ke low, v il , thus freezing the internal clock, and extending data read and write operations. 4.11 auto refresh command the auto refresh command is used to put the device in auto refresh mode (see section 3.5: auto refresh and figure 24: auto refresh ). 4.12 self refresh command the purpose of the self refresh command is used to put the device in self refresh mode to retain and refresh the data contained in the low-power sdram memory array. in self refresh mode, the low-power sdram runs refresh cycles asynchronously. the self refresh cycle is performed according to the extended mode register bits emr0 to emr2 that configure the part of the memory array being refresh (partial array self refresh). for more information on how the command is issued, refer to figure 25: self refresh . 4.13 power-down command the power-down command is used to put the device in power-down mode where the operating current is reduced to the standby current. all banks must be precharged and a minimum time of t rp must elapse before issuing the power-down command. 4.14 deep power-down command the deep power-down command is used to switch the low-power sdram to deep power- down mode. this mode provides maximum power reduction as it cuts the power of the entire memory array of the device. for more information on how the command is issued and its exit sequence, see section 3.7: deep power-down , figure 26: deep power-down entry ac waveforms , and figure 27: deep power-down exit ac waveforms .
commands M65KA128AE 18/53 table 3. commands command ke n-1 ke n (1) e (1) ras (1) cas (1) w (1) udqm/ ldqm (1) dq0- dq15 (1) addr (1)(2) a10 (1) ba0- ba1 (1) mode register set (3) v ih xv il v il v il v il x x op code extended mode register set (3) v ih xv il v il v il v il x x op code bank (row) activate v ih xv il v il v ih v ih x x row address v read v ih xv il v ih v il v ih v il x column v il v read with auto precharge v ih xv il v ih v il v ih v il x column v ih v write v ih xv il v ih v il v il v il x column v il v write with auto precharge v ih xv il v ih v il v il v il x column v ih v precharge all banks v ih xv il v il v ih v il xxxv ih x precharge selected bank v ih xv il v il v ih v il xxxv il v burst stop v ih v ih v il v ih v ih v il xx x x clock suspend entry v ih v il xx x x x x x x clock suspend exit v il v ih xx x x x x x x data mask / output enable v ih xx x x x v il valid x x data mask / output disable v ih xx x x x v ih high-z x x auto-refresh v ih v ih v il v il v il v ih xx x x self-refresh entry v ih v il v il v il v il v ih xx x x self-refresh exit (4) v il v ih v ih xxxx xxx v il v ih v ih v ih x power-down entry v ih v il v ih xxxx xxx v il v ih v ih v ih x power-down exit v il v ih v ih xxxx xxx v il v ih v ih v ih x deep power-down entry v ih v il v il v ih v ih v il xx x x deep power-down exit v il v ih xx x x x x x x 1. x = don?t care (v il or v ih ), v = valid data. 2. addresses a0 to a11 except a10. 3. ba1 and ba0 must both be set to ?0? to issue the mode register set command, and to ?1? and ?0?, respectively, to issue the extended mode register set command. 4. the self-refresh mode is exited by a synchronously driving ke from low to high.
M65KA128AE register descriptions 19/53 5 register descriptions 5.1 mode register description the mode register is used to select the cas latency (2 or 3), the burst type (sequential, interleaved), the burst length (1-, 2-, 4-, 8-word width or full page). it is loaded by issuing a mode register set command that programs a0 to a11 address bits. the values placed on the address lines are then latched into the mode register. ba0-ba1 must be set to ?0?. see table 4: mode register definition , for more details. 5.2 burst length bits (mr0 to mr2) bits 0 to 2 (mr0 to mr2) of the mode register are used to configure the burst length. the burst length is the number of words that are output or input during a read or a write operation, respectively. it can be set to 1, 2, 4, 8 words or full page. 5.3 burst type bit (mr3) bit 3 (mr3) of the mode register is used to set the burst type. the burst type defines the order in which the address locations are accessed during a burst operation. it can be either sequential or interleaved. the type of application microprocessor must be taken into account when selecting the burst type: some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. both burst types support burst length of 1, 2, 4 or 8 words. full page burst is also available when the sequential burst type is selected. 5.4 cas latency bits (mr4 to mr6) the cas latency is the most critical of the mode register parameters. it defines the number of clocks cycles between the detection of a read command to the first data output valid. it can be set to two or three clock cycles. the value of this parameter is determined by the frequency of the clock and the speed grade of the device.
register descriptions M65KA128AE 20/53 5.5 extended mode re gister description the extended mode register is used to configure the low-power self-refresh operation of the device (pasr, ds). it is used to select the area of the memory array refreshed during partial array self refresh operations, and the driver strength. it is loaded by issuing a extended mode register set command that programs a0 to a11 address bits. the values placed on the address lines are then latched into the extended mode register. ba0 and ba1 must be set to ?0? and ?1? respectively. see table 5: extended mode register definition , for more details. 5.5.1 partial array self refresh bits (emr0-emr2) bits emr0 to emr2 of the extended mode register allow to configure the amount of memory that will be refreshed during a self refresh operation (see section 3.4: self refresh ). it can be set to: all banks (banks 0, 1, 2, and 3) two banks (banks 0 and 1) one bank (bank 0) it is important to note that the data stored in the banks or portion of banks which are not refreshed, are lost. as an example, data stored in banks 1, 2 and 3 are lost when the pasr is set to one bank (bank 0 refreshed). table 4. mode register definition address bits mode register bit register description value description a11-a7 - - 00000 a6-a4 mr6-mr4 cas latency bits 010 2 clock cycles 011 3 clock cycles (1) other configurations reserved a3 mr3 burst type 0 sequential 1 interleaved a2-a0 mr2-mr0 burst length bit 000 1 word (a3 is don?t care) 001 2 words (a3 is don?t care) 010 4 words (a3 is don?t care) 011 8 words (a3 is don?t care) 111 full page if a3 = 0 reserved if a3 = 1 other configurations reserved ba1-ba0 - - 00 1. at the maximum clock frequency, the cas latency must be set to 3.
M65KA128AE register descriptions 21/53 5.5.2 driver strengt h bit (emr5-emr6) extended mode register bits, emr5 and emr6, can be used to select the driver strength of data outputs. this value should be set according to the application requirements. 5.5.3 automatic temperature compensat ed self refresh bits(emr3-emr4) the M65KA128AE has a built-in temperature sensor that controls automatically the internal self refresh rate. table 5. extended mode register definition address bits mode register bi t description value description a11-a10 - - 00 a9 emr9 automatic temperature compensated self- refresh (atcsr) 0enabled 1reserved a8-a7 - - 00 a6-a5 emr6-emr5 driver strength bits 00 full strength 01 1/2 strength 10 1/4 strength 11 1/8 strength a4-a3 - - 00 a2-a0 emr2-emr0 partial array self- refresh bits 000 all banks 001 two banks (ba1=0) 010 one bank (ba0 and ba1 =0) other configurations reserved ba1-ba0 - - 10
maximum rating M65KA128AE 22/53 6 maximum rating stressing the device above the ratings listed in table 6: absolute maximum ratings , may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 6. absolute maximum ratings symbol parameter value unit min max t j operating junction temperature ? 25 90 c t stg storage temperature ? 55 125 c v io input or output voltage ? 0.5 2.3 v v dd , v ddq supply voltage ? 0.5 2.3 v i os short circuit output current 50 ma p d power dissipation 1.0 w
M65KA128AE dc and ac parameters 23/53 7 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 7: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match th e measurement conditions when relying on the quoted parameters. figure 3. ac measurement i/o waveform table 7. operating and ac measurement conditions symbol parameter (1)(2) 1. t j = 25c, f = 1mhz 2. all voltages are referenced to v ss = 0v. min max units v dd supply voltage 1.7 1.95 v v ddq input/output supply voltage 1.7 1.95 v t j operating junction temperature ? 25 90 c c l load capacitance 30 pf t r , t f input rise/fall time 0.5 ns v il input pulses low voltage 0.2 v v ih input pulses high voltage 1.6 v v ref input and output timing ref. voltages 0.9 v ai08009c 1.6v input timing reference voltage 0.2v v ddq /2 v ddq output transition timing reference voltage 0v v ddq /2
dc and ac parameters M65KA128AE 24/53 figure 4. ac measurement load circuit table 8. capacitance symbol parameter signal M65KA128AE (1) 1. t j = 25c, f = 1mhz unit min. max. ci1 input capacitance k2.04.5pf ci2 a0-a11, ba0, ba1, ke, e , ras , cas , w , udqm, ldqm 2.0 4.5 pf c io data i/o capacitance dq0-dq15 3.5 6.0 pf table 9. dc characteristics 1 symbol parameter test condition (1) 1. these parameters are measured in t he temperature conditions specified in table 7 . M65KA128AE unit min. max. i li input leakage current 0v v in v ddq (2) ? 22a i lo (2) 2. data outputs are disabled. output leakage current 0v v out v ddq ? 1.5 1.5 a v il (2) input low voltage v in = 0v ? 0.3 (3) 3. v il (min.) = ?0.5v (pulse width 5ns) 0.3 v v ih (4) 4. v ddq must not exceed the level of v dd . input high voltage v in = 0v 0.8 v ddq v ddq + 0.3 (5) 5. v ih (max.) = 2.3v (pulse width 5ns) v v ol output low voltage i out = 100a v in = 0v 0.2 v v oh output high voltage i out = ?100a v in = 0v v ddq ? 0.2 v ai12109b c l device under test
M65KA128AE dc and ac parameters 25/53 table 10. dc characteristics 2 (1) 1. cl stands for cas latency. symbol parameter test condition (2) 2. these parameters are measured in t he temperature conditions specified in table 7 . max. unit i dd1 (3)(4) 3. i dd1 and i dd4 depend on output loading and cycle rates. specif ied values are measured with the output open. they are measured on condition that the addresses are changed only once during t ck (min.). 4. i dd1 and i dd4 depend on output loading and cycle rates. specif ied values are measured with the output open. operating current burst length = 1, one bank active t rc t rc (min), i ol = 0ma 45 ma i dd2p precharge standby current in power-down mode ke v il (max), t k = t k(min) 0.8 ma i dd2ps ke v il (max), t k = 0.6 i dd2n precharge standby current in non power-down mode ke v ih (min), e v ih (min), t k = t k(min) , input signals changed once in 2 clock cycles 4 ma i dd2ns ke v ih (min), t k = input signals are stable 2 i dd3p active standby current in power- down mode ke v il (max), t k = t k(min) 3.0 ma i dd3ps ke v il (max), t k(min) = 1.2 i dd3n active standby current in non power-down mode ke v ih (min), e v ih (min), t k = t k(min) , input signals changed once in 2 clock cycles 10 ma i dd3ns ke v ih (min), t k = input signals are stable 7 i dd4 (3)(4) burst mode current cl = 2 t k t k (min), i ol = 0ma all banks active 50 ma cl = 3 80 i dd5 (5) 5. i dd5 is measured on condition that the add resses are changed only once during t ck (min.). the minimum value of t rc (ras cycle time for refresh operations) is shown in table 13: ac characteristics 2 . auto-refresh current t rrc t rrc (min), all banks active 55 ma i dd6 (6) 6. i dd6 is measured on condition that the device is in self refresh mode long enough after a read and write operations, and the specified t j is respected. self-refresh current ke 0.2v see ta b l e 1 1 a i dd7 standby current in deep power- down mode ke 0.2v 10 a
dc and ac parameters M65KA128AE 26/53 table 11. self-refresh current (i dd6 ) values in normal operating mode temperature (c) memory array (1) 1. these parameters are measured in t he temperature conditions specified in table 7 . unit 4 banks 2 banks 1 bank typ max typ max typ max 70 t j 90 250 200 160 a 40 t j 70 200 170 150 a ?25 t j 40 160 150 140 a table 12. ac characteristics 1 (1)(2) 1. these parameters are measured in the operating and ac conditions specified in table 7 . 2. cl stands for cas latency. symbol alt. parameter min. max. unit t ck t ck clock cycle time cl = 3 7.5 ns cl = 2 15 ns t chw t ch clock high pulse width 2.5 - ns t clw t cl clock low pulse width 2.5 - ns t ac t ac access time from clock cl = 3 - 6 ns cl = 2 - 8 ns t oh t oh data-out hold time 2.0 - ns t ds (3) 3. if t t is greater than 0.5ns (t t -0.5) or ((t r +t f )/2-0.5) should be added t ds data-input setup time 1.9 - ns t dh (3) t dh data-input hold time 0.9 - ns t as t as address setup time 1.9 - ns t ah t ah address hold time 0.9 - ns t cks t cks clock enable setup time 1.9 - ns t cksp t cksp clock enable setup time (power-down exit) 1.9 - ns t ckh t ckh clock enable hold time 0.9 - ns t cs t cms command setup time 1.9 - ns t ch t cmh command hold time 0.9 - ns t olz t lz clock to data output in low-z time 0 - ns t ohz t hz clock to data outp ut in high-z time cl = 3 0 6 ns cl = 2 0 8 ns
M65KA128AE dc and ac parameters 27/53 table 13. ac characteristics 2 (1)(2) 1. these parameters are measured in the operating and ac conditions specified in table 7 . 2. cl stands for cas latency. symbol alt. parameter min. max. unit t rc t rc ras cycle time (normal operation) 75 - ns t rc1 t rc1 ras cycle time (refresh operation) 105 - ns t rc2 t rc2 ras cycle time (self refresh exit to refresh or bank/row activate command) 120 - ns t rcd t rcd delay time, ras active to cas active 30 - ns t ras t ras ras active time 52.5 120,000 ns t rp t rp ras precharge time 22.5 - ns t rrd t rrd delay time, ras active to ras bank active 2 - (3) 3. the unit is the system clock cycle time. t dpl t dpl delay time, write command to data input 2 - (3) t dal t dal data input valid to precharge command cl = 3 2t ck +22.5 ns cl = 2 ns t mrd t rsc mode register set cycle time 2 - (3) t ref t ref refresh time - 64 ms t t t t transition time 0.5 30 ns
dc and ac parameters M65KA128AE 28/53 figure 5. chip enable signal during read, write and precharge 1. the chip enable signal, e , must be issued at a minimum rate with respect to the other signals. 2. burst length = 4 words, latency = 3 clock cycles. 3. raa = address of row a in bank a, caa = address of column a in bank a, qaan= data n r ead from column a in bank a, daan= data n written to column a in bank a. a10 k hi-z dq n ai09959b w qaa1 qaa2 qaa3 qaa4 dab1 dab2 dab3 dab4 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa low ldqm/ udqm dq0-dq15 high bank/row activate in bank a read from bank a write in bank a precharge bank a low low raa caa cab
M65KA128AE dc and ac parameters 29/53 figure 6. read with precharge ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. a10 dq0-dq15 k tck hi-z dq n ai09934b w dq n+1 dq n+2 dq n+3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ke e ras cas ba0 ba1 address ldqm/ udqm tchw tclw tcks tcs tch tckh tas tah trcd tras trp trc bank/row activate in bank a read from bank a precharge in bank a bank/row activate in bank a tac tolz toh tohz low
dc and ac parameters M65KA128AE 30/53 figure 7. read with auto precharge ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. a10 dq0-dq15 k tck hi-z dq n ai09935b w dq n+1 dq n+2 dq n+3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ke e ras cas ba0 ba1 address ldqm/ udqm tchw tclw tcks tcs tch tckh tas tah trcd tras, trrd trc bank/row activate in bank c read with auto precharge from bank c bank/row activate in bank d bank/row activate in bank c tac tolz toh auto precharge start from bank c tohz low
M65KA128AE dc and ac parameters 31/53 figure 8. clock suspend during burst read ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of column a in bank a, qaan= data n read from column a in bank a. a10 k hi-z ai09949 w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 ke e ras cas ba0 ba1 address low ldqm/ udqm dq0-dq15 bank/row activate in bank a read from bank a raa raa caa qaa1 qaa2 qaa3 qaa4 clock suspended during 1 cycle clock suspended during 2 cycles clock suspended during 3 cycles end of read hi-z
dc and ac parameters M65KA128AE 32/53 figure 9. random column read ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of column a in bank a, qamn= data n read from column m in bank a. a10 k hi-z dq n ai09955 w qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa cab raa raa caa cac low ldqm/ udqm dq0-dq15 high bank/row activate in bank a read from bank a precharge in bank a bank/row activate in bank a read from bank a read from bank a read from bank a
M65KA128AE dc and ac parameters 33/53 figure 10. random row read ac waveforms 1. burst length = 8 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of colu mn a in bank a, qamn= data n read from row m in bank a. a10 k hi-z ai09957 w qba1 qba2 qba5 qba6 qba7 qba8 qaa1 qaa2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address rba rba cba raa rbb rbb cbb caa low ldqm/ udqm dq0-dq15 high bank/row activate in bank b read from bank b precharge in bank b bank/row activate in bank b bank/row activate in bank a read from bank a raa qaa3 qaa4 qaa5 qaa6 qaa7 qba3 qba4 read from bank a
dc and ac parameters M65KA128AE 34/53 figure 11. column interleaved read ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of column a in bank a, qamn= data n read from column m in bank a. a10 k hi-z dq n ai12720 w qaa1 qaa2 qaa3 qaa4 qda1 qda2 qdb1 qdb2 qdc1 qdc2 qab1 qab2 qab3 qab4 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa rda rda cda cdc cab cdb high low bank/row activate in bank a read from bank a precharge in bank d read from bank d read from bank d bank/row activate in bank d read from bank d read from bank a precharge in bank a ldqm/ udqm dq0-dq15
M65KA128AE dc and ac parameters 35/53 figure 12. burst column read followed by auto precharge ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of column a in bank a. a10 k hi-z dq n ai09961 b w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa rda rda cda rdb cdb cab high low bank/row activate in bank a read from bank a bank/row activate in bank d read + auto precharge from bank d bank/row activate in bank d read + auto precharge from bank a read + auto precharge from bank d ldqm/ udqm dq0-dq15 rdb auto precharge from bank d autoprecharge start from bank a
dc and ac parameters M65KA128AE 36/53 figure 13. write ac waveforms 1. burst length = 4 words. a10 k hi-z dq n ai09947 w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 ke e ras cas ba0 ba1 address low ldqm/ udqm dq0-dq15 auto precharge start from bank c bank/row activate in bank c write + auto precharge to bank c bank/row activate in bank b write to bank b bank/row activate in bank c precharge in bank b bank/row activate in bank b tcks tckh tcs, tas tch, tah tds tdh trcd tdal trc trrd trcd tdpl trp tras trc
M65KA128AE dc and ac parameters 37/53 figure 14. byte write ac waveforms 1. burst length = 4 words. hi-z dq8-dq15 bank/row activate in bank d udqm a10 k hi-z ai09963b w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address ldqm dq0-dq7 high read from bank d lower byte read upper byte read upper byte write lower byte write upper byte write read from bank d upper byte read upper byte read
dc and ac parameters M65KA128AE 38/53 figure 15. mode register set ac waveforms 1. to program the extended mode register, ba0 and ba1 must be set to ?0? and ?1? respectively, and a0 to a11 to the extended mode register data. 2. mr data is the value to be written to the mode register. a10 dq0-dq15 k hi-z ai09948 w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ke e ras cas ba0 ba1 address ldqm/ udqm high tmrd, 2 clock cycles (min) mr data (2) trp precharge all banks mode register set bank/row activate valid
M65KA128AE dc and ac parameters 39/53 figure 16. clock suspend during burst write ac waveforms 1. raa = address of row a in bank a, caa = address of column a in bank a, daan= data n written to column a in bank a. a10 k hi-z ai09950b w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 ke e ras cas ba0 ba1 address low ldqm/ udqm dq0-dq15 bank/row activate in bank a write to bank a raa raa caa daa1 daa2 daa3 clock suspended during 1 cycle clock suspended during 2 cycles clock suspended during 3 cycles daa4
dc and ac parameters M65KA128AE 40/53 figure 17. random column write ac waveforms 1. burst length = 4 words. 2. rda = address of row a in bank d, cda = address of column a in bank d, ddmn= data n written to column m in bank d. a10 k hi-z dq n ai09956 w dda1 dda2 dda3 dda4 ddb1 ddb2 ddc1 ddc2 ddc3 ddc4 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address rda rda cda cdb rdd rdd cdd cdc low ldqm/ udqm dq0-dq15 high bank/row activate in bank d write to bank d precharge in bank d bank/row activate in bank d write to bank d write to bank d write to bank d ddd1 ddd2
M65KA128AE dc and ac parameters 41/53 figure 18. random row write ac waveforms 1. burst length = 8 words. 2. raa = address of row a in bank a, caa = address of column a in bank a, damn= data n written to row m in bank a. a10 k hi-z ai09958 w daa1 daa2 daa5 daa6 daa7 daa8 dda1 dda2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa rda rab rab cab cda low ldqm/ udqm dq0-dq15 high bank/row activate in bank a write to bank a precharge in bank a bank/row activate in bank a bank/row activate in bank d write to bank a rda dda3 dda4 dda5 dda6 dda7 daa3 daa4 dda8 write to bank d dab1 dab2
dc and ac parameters M65KA128AE 42/53 figure 19. column interleaved write ac waveforms 1. burst length = 4 words. 2. raa = address of row a in bank a, caa = address of column a in bank a, damn= data n written to column m in bank a. a10 k hi-z dq n ai09521 w daa1 daa2 daa3 daa4 dba1 dba2 dbb1 dbb2 dbc1 dbc2 dab1 dab2 dbb1 dbb2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa rba rba cba cbc cab cbb high low bank/row activate in bank a write to bank a write to bank b write to bank b bank/row activate in bank b write to bank b write to bank a precharge in bank a ldqm/ udqm dq0-dq15 cbd dbb3 dbb4 write to bank b precharge in bank b
M65KA128AE dc and ac parameters 43/53 figure 20. burst column write followed by auto precharge ac waveforms 1. burst length = 4 words 2. raa = address of row a in bank a, caa = address of column a in bank a. a10 k hi-z dq n ai09962 w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa rda rda cda rdb cdb cab high low bank/row activate in bank a write + auto precharge from bank a bank/row activate in bank d write to bank a write + auto precharge from bank d ldqm/ udqm dq0-dq15 rdb auto precharge start from bank a auto precharge start from bank d bank/row activate in bank d write + auto precharge from bank d
dc and ac parameters M65KA128AE 44/53 figure 21. precharge termination 1. burst length = 8 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of column a in bank a, qaan= data n r ead from column a in bank a, daan= data n written to column a in bank a. rac rac a10 k hi-z dq n ai09524 w t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ke e ras cas ba0 ba1 address raa raa caa rab cab high rab ldwm/ udqm write masking dq0-dq15 daa1 daa2 daa3 daa4 daa5 dq n qab1 qab2 qab3 qab4 trcd tras bank/row activate in bank a write to bank a precharge in bank a + write terminated bank/row activate in bank a tdpl trp tras read from bank a precharge in bank a + read terminated bank/row activate in bank a
M65KA128AE dc and ac parameters 45/53 figure 22. power-on sequence 1. mr data and emr data are the values to be written to t he mode register and the extended mode register, respectively. mr data (1) a10 k ai09960b w t0 t1 t2 t3 t4 t5 t6 t9 t10 t11 t12 t13 t8 t14 t15 t16 t17 ke e ras cas ba0 ba1 address ldqm/ udqm t18 t19 t20 hi-z dq0-dq15 bank/row activate t7 t21 precharge all banks cbr auto refresh 1 clock cycle needed 2 refresh cycles needed emr data (1) high level nedeed high mode register set extended mode register set cbr auto refresh tmrd tmrd trp trc1 trc1
dc and ac parameters M65KA128AE 46/53 figure 23. power-down mode and clock masking ac waveforms 1. burst length = 4 words, latency = 3 clock cycles. 2. raa = address of row a in bank a, caa = address of column a in bank a, qaan= data n read from column a in bank a. qaa1 qaa2 qaa3 qaa4 a10 k ai09951 w t0 t1 t2 t3 t4 t5 t6 t7 t9 t10 t11 t12 t13 t6 t7 t8 t14 t15 t16 t17 ke e ras cas ba0 ba1 address low ldqm/ udqm raa raa caa t18 t19 t20 t21 hi-z dq0-dq15 bank/row activate in bank a read from bank a start of clock masking power-down entry power-down exit active standby end of clock masking precharge in bank a power-down entry power-down exit precharge standby tcksp tcksp
M65KA128AE dc and ac parameters 47/53 figure 24. auto refresh a10 k ai09952c w t0 t1 t2 t3 t4 t5 t6 tn+2 tn+3 tn+4 tn+5 tn+6 tn+1 tm tm+1 tm+2 tm+3 ke e ras cas ba0 ba1 address low ldqm/ udqm tm+4 tm+5 tm+6 hi-z dq0-dq15 precharge (optional) bank/row activate read tn tm+7 high auto refresh auto refresh trp trc1 trc1
dc and ac parameters M65KA128AE 48/53 figure 25. self refresh a10 k ai09953b w t0 t1 t2 t3 t4 tn+2 tm tm+1 tn+1 tk ke e ras cas ba0 ba1 address low ldqm/ udqm tk+1 tk+2 tk+3 hi-z dq0-dq15 precharge (optional) tn tk+4 self refresh entry self refresh exit self refresh entry ( or bank/row activate) next clock enable self refresh exit bank/row activate next clock enable trp trc2 trc2
M65KA128AE dc and ac parameters 49/53 figure 26. deep power-down entry ac waveforms 1. ba0, ba1 and address bits a0 to a11 (except a10) are ?don?t care?. a10 dq0-dq15 hi-z k ke e ras cas w ai07720c precharge all banks (optional) deep power-down entry t0 t1 t2 t3 t4 t5 trp
dc and ac parameters M65KA128AE 50/53 figure 27. deep power-down exit ac waveforms 1. mr data and emr data are the values to be written to t he mode register and the extended mode register, respectively. 1 mr data (1) a10 k ai09954c w t0 t1 t2 t3 t4 t5 t6 t9 t10 t11 t12 t13 t8 t14 t15 t16 t17 ke e ras cas ba0 ba1 address ldqm/ udqm t18 t19 t20 hi-z dq0-dq15 deep power-down exit bank/row activate t7 t21 precharge all banks auto refresh 1 clock cycle needed 2 refresh cycles needed emr data (1) high level nedeed high 200s mode register set extended mode register set auto refresh tmrd tmrd trp trc1 trc1
M65KA128AE part numbering 51/53 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 14. ordering information scheme example: m65ka128a e 8 w 5 device type m65 = low- power sdram architecture k = bare die operating voltage a = v dd = v ddq = 1.8v, standard lpsdram, x16 array organization 128 = 4 banks x 2mbit x 16 option 1 a = one chip enable option 2 e = e die speed 8 = 7.5ns (133mhz) package w = unsawn wafer temperature range 5 = ?25 to 90c
revision history M65KA128AE 52/53 9 revision history table 15. document revision history date revision changes 03-apr-2005 0.1 initial release. 8-aug-2006 1 updated maximum clock frequency. renamed burst terminate command to burst stop. updated to datasheet status.
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